1. Field of the Invention
The present invention relates to a static type semiconductor memory device (SRAM: Static Random Access Memory) and, more specifically, to a structure of connection between conductive layers in the SRAM.
2. Description of the Background Art
There is a kind of memory cell of the SRAM which includes two access MOS (Metal Oxide Semiconductor) transistors, two driver MOS transistors and two load MOS transistors. In such a memory cell, a flip-flop circuit is formed with the two load MOS transistors and two driver MOS transistors.
Two storage nodes cross-coupled by the flip-flop circuit are formed. The two storage nodes have a bistable state of (H (high) level, L (low) level) or (L level, H level). The bistable state is maintained as long as a prescribed power supply potential is provided.
Generally, a source or a drain of each MOS transistor described above is connected to an upper-layer interconnection. The upper-layer interconnection can connect to the source or drain via a contact hole. Conventional contact holes, each connecting an upper-layer interconnection and a substrate, are implemented with various shapes.
Japanese Patent Laying-Open No. 1-256152, for example, describes a semiconductor device having an interlayer insulator film provided with a contact hole having, at least on its portion, a sidewall which is tapered from the bottom to the surface.
Japanese Patent Laying-Open No. 10-270555 also describes a semiconductor device including an interlayer insulator film formed on an underlying layer of semiconductor with a plurality of layers having different etching rates and a contact formed in an opening provided in the interlayer insulator film and reaching the underlying layer of semiconductor, wherein the contact is expanded in a radial direction in a portion of the interlayer insulator film adjacent to the underlying layer of semiconductor.
Japanese Patent Laying-Open No. 2-142161 also describes a semiconductor device in which a concave and convex portion is formed on a sidewall of a removal portion which is formed by selectively removing a portion of an insulator film provided on a substrate, and a metal film provided on the removal portion engages with the insulator film.
On the other hand, a phenomenon in which a memory state is inverted (this phenomenon is referred to as a xe2x80x9csoft errorxe2x80x9d hereafter) may occur with flow or injection of charge between a storage node and a substrate by carriers generated by an xcex1 ray due to a size reduction of the SRAM, a decrease in an operation voltage or a decrease in a storage node capacity.
One of measures against this soft error is to add a capacity to a storage node. It is expected that, by increasing a capacity between the storage node and a ground or between the storage node and a voltage supply unit, for example, a ratio of a change in charge to the storage node by the a ray is decreased, and thus the soft error can be reduced.
Therefore, an object of the present invention is to provide a static type semiconductor memory device highly resistant to a soft error by adding a capacity to a storage node.
A static type semiconductor memory device according to the present invention includes a memory cell, first and second conductive portions formed within the memory cell, an interlayer insulator film covering the first and second conductive portions, first and second connection holes provided in the interlayer insulator film and reaching the first and second conductive portions, first and second plug portions formed within the first and second connection holes, and third and fourth conductive portions respectively formed on the first and second plug portions. A space between the first and second connection holes located in the interlayer insulator film is made smaller than that between the first and second connection holes on a surface of the interlayer insulator film.
According to the present invention, a space between the first and second plug portions formed in the interlayer insulator film can be made smaller because the space between the first and second connection holes located in the interlayer insulator film is made smaller than the space between the first and second connection holes on the surface of the interlayer insulator film. With this, a capacity between desired first and second plug portions within a memory cell can increase, and as a result, a capacity can be added to a storage node. Therefore, resistance to the soft error can be enhanced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.